Cadence Encounter Platform Enables Toshiba to Produce World's Fastest Synthesizable 64-Bit MIPS CPU Core

RTL Compiler and NanoRoute Ultra Router Deliver Record CPU Performance for ASSP/SoC Products

Using RTL Compiler synthesis, Toshiba dramatically improved timing performance on its previous generation set-top box design. It also provided better interconnect structure to ease back-end design closure and meet Toshiba's aggressive performance goals. For physical implementation Toshiba employed the full complement of NanoRoute Ultra features, including concurrent routing, and timing and signal integrity (SI) optimization to maximize the performance achieved in RTL synthesis. Signal integrity issues, and their impact on delay, were addressed during routing itself for a smooth route to silicon.

"NanoRoute Ultra simply amazed me," said Andy Le, director of Physical Design and Methodology at TAEC's TX RISC Business Unit. "It is always a challenge to close on timing during physical implementation, so given the superior results we obtained from RTL Compiler synthesis; we feared any potential timing closure issues or performance degradation in the back-end might be magnified. However, by incorporating NanoRoute Ultra's multi-CPU routing into our design flow, we were able to route the design to completion very quickly. Not only did timing close right away, but we also maintained the incredible performance boost we achieved from RTL Compiler synthesis through final routing.

"NanoRoute Ultra also demonstrated significant value for us with its ability to address signal integrity issues completely on the fly. NanoRoute's routing-centric wire spacing, layer selection, net ordering and overall topology control SI closure enabled us to produce a totally clean final result that correlated with Cadence CeltIC SI analysis at final sign-off. We could not have achieved these results with any other router."

"It was a pleasure to work with Cadence on integrating NanoRoute Ultra into our design flow," said Shardul Kazi, vice president of TAEC's TX RISC Business Unit. "Improving design cycle time of multi-million gate designs is always our challenge. The Cadence RTL-to-GDS technology helps us design our high-performance Application Specific Standard Products (ASSPs) and custom System-on-Chip (SoC) designs with embedded MIPS RISC CPU cores."

"We are very pleased that our Encounter technology with the new RTL Compiler synthesis has demonstrated significant benefits to Toshiba's advanced design flow -- dramatically better performance results, with significant savings in design cycle time," said Ping Chao, senior vice president and general manager, Chip Implementation at Cadence. "RTL Compiler synthesis and NanoRoute Ultra provide unparalleled technology for the nanometer era and we look forward to continuing to contribute to Toshiba's success."

About Cadence

Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks and Encounter, NanoRoute, and RTL Compiler are trademarks of Cadence Design Systems, Inc. All other trademarks are property of their respective holders.

CONTACT: Cadence Design Systems, Inc.
             Judy Erkanat, 408/894-2303
             jerkanat@cadence.com